The disclosed embodiments relate to a non-volatile memory device and a fabrication method thereof, and more particularly, to a vertical channel type non-volatile memory device and a fabrication method thereof.
A non-volatile memory device maintains data stored therein although a power supply is cut off. As the current technology reaches its limitation in improving the integration degree of a memory device having a two-dimensional structure where a memory device is fabricated in a single layer over a silicon substrate, a non-volatile memory device having a three-dimensional structure where memory cells are stacked vertically over a silicon substrate is desired.
Hereafter, a method for fabricating a typical non-volatile memory device having a three-dimensional structure and problems thereof will be described in detail with reference to the accompanying drawings.
FIGS. 1A to 1C are perspective views illustrating a process of fabricating a typical vertical channel type non-volatile memory device. Referring to FIG. 1A, a source region S is formed in a substrate 10. Subsequently, a lower selection transistor (LST), a plurality of memory cells MC, and an upper selection transistor (UST) are sequentially stacked along each channel CH protruding from the substrate 10 with the source region S formed therein.
Herein, channels CH are buried in a plurality of interlayer dielectric layers 11 and a plurality of conductive layers 12 for a gate electrode that are alternately formed on each other. Also, although not illustrated in the drawing, a gate insulation layer is interposed between the channels CH and the conductive layers 12 for a gate electrode of the lower selection transistor and the upper selection transistor. Also, a charge blocking layer, a charge trapping layer, and a tunnel insulation layer are interposed between the channels CH and the conductive layers 12 for a gate electrode of the memory cells MC.
As described above, the plurality of memory cells MC connected in series between the upper selection transistor and the lower selection transistor form one string, and the string is disposed vertically with respect to the substrate 10.
Referring to FIG. 1B, a plurality of memory blocks MB are separated one from another by etching the plurality of the interlayer dielectric layers 11 and the conductive layers 12 for a gate electrode thereby forming etched interlayer dielectric layers 11A and etched conductive layers 12A, respectively. Herein, a plurality of strings constituting the memory blocks MB are coupled in parallel with the source region S.
Referring to FIG. 1C, the plurality of the interlayer dielectric layers 11A and the plurality of the conductive layers 12A for a gate electrode are patterned in tiers, such that surfaces of each of the plurality of the conductive layers 12 for a gate electrode are exposed. The exposure is intended to form contact plugs to be coupled with the surfaces of the plurality of the conductive layers 12 for a gate electrode in a subsequent process. The patterned interlayer dielectric layers 11A and the patterned conductive layers 12A are referred to as interlayer dielectric layer patterns 11B and conductive layer patterns 12B, hereafter. Accordingly, the plurality of the conductive layer patterns 12B are exposed in each layer.
Although not illustrated in the drawing, a process for forming contact plugs, bit lines, and word lines is subsequently performed.
According to the conventional technology described above, the integration degree of a memory device may be improved by stacking a plurality of memory cells MC along the channels CH protruding vertically with respect to the substrate 10.
However, the lower selection transistor, the memory cells MC, and the upper selection transistor are formed after the plurality of the interlayer dielectric layers 11 and the conductive layers 12 for a gate electrode are alternately stacked. Thus, a gate electrode including a silicide layer cannot be formed.
In other words, since the material for forming the conductive layers 12 for a gate electrode is limited to a polysilicon layer, there is a limitation in reducing the resistance of a source select line, a word line, and a drain select line. Therefore, loading time increases when the memory device is driven, and accordingly, there is concern that the driving speed is decreased.
Also, the high resistance of the source region S decreases the characteristics of the memory device. The conventional technology performs an ion implantation process in the source region S to resolve the problem. However, although the ion implantation process is performed, there is a limitation in decreasing a resistance value of the source region S because the source region S has resistance of hundreds of ohm/unit area. Also, although a method of forming a contact coupled with the source region S is considered to reduce the resistance of the source region S, the object of increasing an integration degree of the memory device is frustrated due to the area needed for forming the contact.